Logical circuits



1966 HAJIME ENOMOTO ETAL 3,292,002

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LOGICAL CIRCUITS United States Patent 3,292,002 LOGICAL CIRCUITS Hajime Enomoto, Ichikawa-shi, and Saburo Slnral, Nerima-ku, Tokyo-to, Japan, assignors to Kokusai Denshin Denwa Kabushiki Kaisha, Tokyo-to, Japan, a joint-stock company of Japan Filed July 13, 1965, Ser. No. 475,308 Claims priority, application Japan, Dec. 30, 1958, 33/383155; Feb. 28, 1959, 34/5,996 Claims. (Cl. 307-88) This invention relates to improvements of logical circuits.

This application is a continuation-in-part of our application, Serial No. 859,612, filed Dec. 15, 1959, now abancloned.

Logical operations of logical circuits utilizing magnetic cores or magnetic elements are very stable, because the mechanical and electrical characteristics of magnetic cores do not vary for a long period of time and are very stable. Moreover, these logical circuits can be embodied as the devices of small size and low cost. Consequently, these logical circuits have been widely studied. The usual logical circuits utilizing magnetic cores can represent the binary digit 1 or 0 in accordance with existence or absence of a pulse. In these logical circuits, for attaining a logical operation with a constant output current, it is necessary that the magnetic cores have strictly rectangular hysteresis characteristics and the hysteresis characteristics of all the magnetic cores forming logical elements are equal as strictly as possible. However, if the cycle of excitation is increased to increase the speed of logical operation, unfavorable temperature rise of the magnetic cores occurs, whereby the rectangularity of the hysteresis characteristic of the magnetic core deteriorates and its operation becomes unstable. Furthermore, in the abovementioned logical circuits, logical elements are necessary for the operation Not among the operations And, Or and Not; electrical connection must be remarkably varied with the variation of the kind of the logical operations; and number of branch lines at the output side is relatively small.

It is an object of this invention to provide a superior logical circuit having no such disadvantages as described above.

It is another object of this invention to provide a superior logical circuit capable of carrying out the logical operation in a sufficiently stable and speed manner even when magnetic cores having incomplete rectangular hysteresis characteristic are used.

Said object and other objects have been attained by the logical circuit of this invention, in which an even number of magnetic cores having substantially rectangular hysteresis characteristics and provided with several kinds of windings or couplings is combined with an even number of rectifying elements; a bridge is formed with said windings and elements; the impedance of one or more than one of the arms of said bridge is made to vary by an input signal having information; and an output signal having a polarity corresponding to the positive or negative polarity of the input signal is obtained. By the circuit of this invention, even though the rectangular characteristics of the various magnetic cores are made to vary somewhat by high-speed operation, it is possible to diminish this effect, because the circuit is in the form of a bridge.

The impedance of said bridge is always constant with respect to its electric source, because the impedance of one of each adjacent arms of said bridge is always higher or lower than that of another of said arms and the impedances of the opposite arms are always equal. Consequently, a constant current flows always into said bridge ice from the electric source. On the other hand, even when the characteristics of the magnetic cores and rectifying elements are varied somewhat with increased speed of the logical operation, relative variation between the impedances of the arms is very minor, whereby speed of the logical operation can be remarkably increased.

A positive or negative output current can be made to flow through the load circuit of a bridge, said load circuit being usually connected with two opposite terminals or ports of said bridge. Consequently, as will be described hereinafter, by reversely connecting said load terminals with the input terminals of the next stage, it is possible to carry out Not operation in a very simple manner. Furthermore, by use of said bridge system, it is possible to make the logical circuit operate in the same manner as usual cases even when a DC. input current or a particular input current which represents 0 or +1, or 0 or 1 depending on whether said current ceases or flows is need (said particular current will be denoted as a single current hereinafter). Furthermore, an output current corresponding to the binary digit 0, +1 or 0, 1 can be taken out by cutting one arm of the bridge to form two terminals at said cut portion and by connecting a load between said terminals.

Furthermore, as will be described in detail hereinafter, it is possible by the application of this invention to increase practically and to an extreme degree the logical operational speed and, at the same, to reduce the number of the necessary circuits for accomplishing the same logical operation, because the logical operation by the circuit of this invention is made to take place in two stages, that is, the input stage and the output stage.

The novel features of this invention are set forth with particularity in the appendant claims, but this invention, both as to its function and operation together with objects and advantages thereof, may be understood by reference to the following description, taken in connection wth the accompanying drawings, in which the same or equivalent parts are designated by the same characters, numerals, symbols, and in which:

FIG. 1 is a schematic connection diagram of one example of this invention;

FIG. 2 is a diagrammatical representation of the driving pulse trains, involving reading pulses and writing-in bias pulses which are used for the logical circuit of FIG. 1;

FIG. 3 is a graphical representation showing a hysteresis lop of the magnetic core to be used for the logical circuits of this invention, and the relation between inputand 9;

FIGS. 5, 8, and 9 are schematic connection diagram of other examples of this invention;

FIG. 6 is a graphical representation showing the driving pulse trains, involving resetting pulses, writing-in bias pulses and reading pulses which are used for the logical circuits of FIGS. 5, 8, and 9;

FIG. 10 is a schematic connection diagram of a shifting register constructed by using the logical circuit of this invention;

FIGS. 11 and 12(a) are schematic connection diagrams of other systems, showing actual applications of the logical circuits of this invention;

FIG. 12(b) is a schematic connection diagram of a modification of the embodiment of FIG. 12(a);

FIG. 12(c) is a schematic connection diagram of a modification of the embodiment of FIG. 5;

FIGS. 13, 15 and 17 are schematic connection diagrams of still other systems, showing actual applications Of the logical circuitsof, this invention, principally the connections for effecting operations in the output circuit sides;

FIGS. 14, 16, and 18 are, respectively, diagrams in which contact points of mechanical relays have been substituted for the output circuits of FIGS. l3, l5, and 17;

FIG. 19 is a schematic connection diagram of a circuit for representing a complex logical function, said circuit being obtained by application of the logical circuit of this invention, and from said circuit being omitted the input, writing-in, bias, and resetting windings;

FIG. 20 is a diagram in which contact points of mechanical relays have been substituted for the output circuit of FIG. 19;

FIG. 21 is a modification of the relay circuit illustrated in FIG. 20;

FIG. 22 is a schematic connection diagram of another circuit for representing another complex logical function, said circuit corresponding to the circuit of FIG. 19;

FIG. 23 is a diagram in which contacts of mechanical relays have been substituted for the output circuit of FIG. 22;

FIG. 24 is a modification of the relay circuit illustrated in FIG. 23; and I FIG. 25 is a schematic connection diagram illustrating the case wherein a high-speed carry detector is composed from the logical circuit of this invention.

Referring to the drawings, FIG. 1 is a connection diagram showing one example of application of the basic circuit of the logical circuit of this invention. FIG, 2 shows the driving pulse train necessary for the operation with the aforesaid circuit. In FIG. 1, ferro-magnetic cores M and M have substantially rectangular hysteresis characteristics such as that of FIG. 3, which are substantially equal. A signal input winding I is wound so that thewinding directions for both magnetic cores will be the same, and a signal pulse current I is made to flow from its input terminals T A writing-in bias winding W is wound in the same direction as the winding I with respect to the core M and in the opposite direction to the winding I with respect to the core M A signal output winding has the dual function as a winding for resetting. To this winding are connected rectifying elements or rectifiers D and D such as for instance diodes, which have been connected in series so as to make the direction of conduction of current the same, to form a closed circuit. Terminals R for impressing driving pulse for resetting are provided at the connection points of the output winding 0 and the rectifying elements, and, furthermore, output terminals T for leading out output signal pulses I are provided at the intermediate portion of the output winding 0 and at the connection point between the rectifying elements.

Now, if a pulse current 1,, which functions dually for resetting drive pulse, is made to flow, as indicated in FIG. 1, from the l-R terminal in the direction, the residual magnetic flux of M and M will become, respectively, the points of Br and +Br (FIG. 3), and the reset condition will be established. (For simplicity, the conditions of +Br and Br shall be represented, respectively, by and hereinafter.) However, when resetting is done in this manner, rectifying elements D and D which are in the regular direction with respect to the reading-out current, to the output winding 0, as may be seen from the illustration. Moreover, the input winding I of the next stage (shown by dotted lines in the illustration) is connected to the output terminals T The values of the impedance of the output winding 0, the resistance of the rectifying elements D and D in the regular direction, and the impedance of the input winding of the next stage are selected suitably by employing a suitable number of turns in said windings in order to pass a sufliciently high pulse current through said output winding 0 to reset the cores M1 and M2.

After the, cores M and M are placed in the and conditions in this manner, the input signal pulse current I is made to flow in the input winding I and, simultaneously, a writing-in bias pulse current I of -a magnitude adapted to produce a peaked magnetic field in each core, said field being substantially equal to the coercive force H (FIG. 3) of the core, is made to flow in the writing-in bias Winding W from the to the direction. Although, in the above case, a magnetic field which is approximately equal to H is imparted by said writing-in bias pulse current, in the I- direction with respect to the core M and in the direction with respect to the core M when, at the same time, the input signal pulse current 1,, of positive polarity as indicated by solid line in FIG. 1, is added to the winding I the magnetic fields induced in the core M by both the pulse currents I and I are superimposed additively, because the windings I and W are wound in the same direction, whereby a magnetic field of ldirection which is larger than H is imposed upon the core M and the residual polarization of the core M changes from to On the other hand, because the directions of the windings I and W are opposite with respect to the core M the magnetic fields induced in the core M by the two above-mentioned pulse currents are superimposed differentially, whereby the magnetic field imposed upon the core M and having direction becomes smaller than H and the residual polarization of the core W is maintained unchanged in the (1-) condition. Under these conditions, the current which is made to flow through the output circuit by the induced voltage accompanying the change in magnetic flux at this time is completely suppressed by the reverse-direction resistance of the rectifying element D Consequently the writing-in is effected with very high efficiency. Furthermore, in the case where the input signal pulse current I, is of negative polarity as indicated by dotted line in FIG. 1, the magnetic field due to the current I, and that due to the current I have directions which are opposite to that of the aforedescribed case, the polarity of the residual polarization of the core M is retained unchanged in the condition, and the polarity of the residual polarization of the core M changes from to In this case, also, the current which is made to flow through the output circuit by the induced voltage accompanying the change in magnetic flux is completely suppressed by the reverse-direction resistance of the rectifying element D and, consequently, the writingin is effected with high efficiency. As a result, during the writing-in operation, if the input signal pulse current I as to the information signal, is of positive polarity, the polarities of the residual polarizations of the cores M and M assume the conditions of and respectively, and if I, is of negative polarity, they assume the conditions of and respectively.

Next, in order to take out the signal which has been written in, with the condition of the polarity of the residual polarization, in the cores in the above-described manner, a reading-out pulse current 1,, which functions dually as a reset pulse, is made to flow in one direction from the terminal R of polarity. Then, if the writing-in is effected by a positive signal pulse current 1,, and the cores M and M are in the and conditions, the coil 0 of the winding 0 wound on the core M will offer a low impedance with respect to the reading-out pulse current 1,, but the coil 0 of the winding 0 wound on the core M will offer a high impedance. Consequently, a large part of the current I will flow through the path of coil 0 input winding of the next stage (indicated by dotted line), D and an information signal of positive polarity will be read out directly in the input signal winding of the nextstage. At the same time, a certain amount of output current will flow through the coil 0 also, causing the magnetic field of the core M to change from to and the residual polarizations of the cores M and M will return to the reset condition' of and respectively. On the other hand, if writing-in is effected by a negative signal pulse current 1 and the cores M and M are in the and conditions, the coil wound on the core M will offer a high impedance, and the coil 0 wound on the core M will offer a low impedance. Consequently, a large part of the reading-out pulse current I will flow through the path of: D input signal winding of the next stage and coil 0 and an information signal of negative polarity will be read out in the input signal winding of the next stage. At the same time, a certain amount of the output current will flow through the coil 0 also causing the core M to change from to and the aforementioned polarizations will return to the reset condition.

While the process of the logical operation of the circuit shown in FIG. 1 has been described above, it is apparent that each of the magnetic cores performs the action which 7 is extremely similar to that of -a mechanical relay. That is, the input signal winding I of the next stage corresponds to the signal winding or the exciting winding of a mechanical relay, and the output winding 0 corresponds to the contact points of the relay. In the case of FIG. 1, the output coil of the core M corresponds to the break" contact point of the relay, and the output coil of the core M to the make contact point of the relay.

FIG. 4(a) shows a circuit wherein the output circuit of the circuit of FIG. 1 has been replaced by relay contact points, for the case wherein a signal input current of positive polarity is being made to flow. FIG. 4(b) illustrates the case wherein a signal input current of negative polarity is being made to flow. Contact point u has the function of closing or opening depending on whether the input current is positive or negative; and E has the function of opening or closing depending on whether the input current is positive or negative. R and R are, respectively regular direction resistances of the rectifying elements of FIG. 1, and Z is a load impedance which is equivalent to the input impedance of the next stage in the case of FIG. 1.

FIG. 5 illustrates one example of another basic logical circuit of the present invention, in which four sequential magnetic cores M M M and M made of preferably ferro-magnetic material and four rectifiers or rectifying elementsD D D and D are used. By the use of this circuit, it is not necessary to consider the relation between the impedance of the output winding and the impedance of the rectifying elements and input winding of the next stage as in the case of the circuit of FIG. 1.

Consequently, any number of winding turns and any impedance can be selected, whereby the logical operation is made very easy. That is, an input winding I a writing in bias winding W, a reset winding S, and an output winding 0 are so provided, and terminals R, which impart reading-out pulse cur-rent, are so installed between the coils O and 0 of the winding 0 wound, respectively, on the cores M and M and between the coils O and 0 of the winding 0 wound, respectively, on the cores M and M that the cores M and M are caused to perform the same actions as the core M of FIG. 1, and'the cores M and M are caused to perform the same action as the core M of FIG. 1. Furthermore, the rectifying elements D and D are connected in series and placed between said coils O and O in the'direction of flow of the reading-out pulse current, and the rectifying elements D and D are connected in series and placed between the coils O and O in said direction of current flow. In addition, the connecting point of the rectifying elements D to D and that of the rectifying elements D to D are made the output terminals T and are connected to the signal input winding I of the next stage.

The driving pulse train of a basic logical circuit using four magnetic cores and four rectifying elements as described above is represented in FIG. 6. Its action is as follows: When a pulse current I for resetting is made to flow with sufficient magnitude in the direction of from the side to the side of the resetting winding 5, the residual polarizations of the cores M M M and M assume their respective reset conditions of I Next, if a writing-in bias pulse current 1,, is made to flow in the direction of from the side to the side of the winding W, and an input signal pulse current I, is made to flow simultaneously through the input signal winding I writing-in will be effected with the cores M M M and M in the conditions of and respectively, in the case when the current I, is positive and in the reverse conditions of and respectively, in the case when the current I is negative, as described for the circuit of FIG. 1. In order to read out information written in this manner, a pulse current I for reading-out is made to flow through the terminals R from to Then, if the aforesaid magnetic cores have been written in in the conditions of and the coils O and 0 of the winding 0 will offer a high impedance with respect to the current 1,, and the coils O and 0 of the winding 0 will offer a low impedance thereto. Consequently the current I will flow principally through the following path: Coil O D .input winding of the next stage D coil 0 and will send out a reading-out pulse current, as a direct, output pulse current +1 of positive polarity, into the input winding of the next stage. At the same time, a certain amount of the reading-out current will flow also in the high-impedance winding side, the cores M and M will change from the to the condition, and the aforesaid magnetic cores will assume conditions of and respectively.

Conversely, if the aforesaid magnetic cores have been written in the conditions of and respectively, the relative magnitudes of the impedances of the windings of the magnetic cores will be the reverse of those described above, and the current I will flow principally through the path of: Coil O D Input winding of the next stage D Coil O and will send out an information, as an output pulse current -I of negative polarity, to the input winding of the next stage, at the same time, causing the aforesaid magnetic cores to assume conditions of and respectively. After the information has been read out in this manner, the reset pulse current I is made to flow again through the winding S to return the aforesaid magnetic cores to the conditions of and respectively. In this manner, the same operation is repeated to effect, successively, the actions of writing-in, reading out, and resetting.

In the above described case, if the internal impedance of the reading-out pulse source is made sufficiently high, the reaction current due to the voltage induced in the output winding during writing-in is completely suppressed by the reverse resistances of the rectifying elements. Therefore, the writing-in is effected with high efficiency. Furthermore, although voltages are induced in the coils O and 0 of the output winding 0 during resetting, their directions are opposite; therefore, they cancel one another, and, by making the internal impedance of the reading-out pulse source sufiiciently high, the reaction current due to resetting is completely suppressed, whereby resetting can be carried out efliciently. Moreover, this case differs from that utilizing two magnetic cores and two rectifying elements as indicated in FIG. 1 in that the impedance of the output winding can be selected independently of the impedances of the rectifying elements and the input winding of the next stage, and in its advantage of having the possibility of obtaining an output which can be increased freely by increasing the number of turns of the output winding. Consequently, it is possible to design the circuit so as to obtain a relatively large number of the output windings. Moreover, because the rectifying elements function only to suppress the reaction current during writing-in and are installed in the regular direction with respect to the reading-out pulse current I they impose no obstacles whatsoever. Furthermore, it is possible to completely suppress the reaction current which occurs during reading-out from the next sta e and resetting, and to completely effectuate a directional transmission of any information signal.

It is possible to consider the output circuit for the case in which four magnetic cores are used as being substituted by the contact points of mechanical relays in a manner similar to that indicated in FIGS. 4(a) and 4(b). FIG. 7(a) illustrates the case wherein a signal input current of positive polarity has been imposed, and FIG. 7(b) illustrates the case wherein a signal input current of negative polarity has been imposed. As described previously, contact points it and E have the functions of closing or opening depending on the polarity of the input current. However, the rectifying elements have been omitted, because they have no connection with functioning.

While basic examples of the case wherein two magnetic cores are used and the case wherein four magnetic cores are used have been described above, the manner in which the windings W and S are wound may be modified as shown in FIGS. 8 and 9. In either case, exactly the same action will result even though the directions of the currents I and I are reversed. Moreover, it is apparent that, if the directions of the currents I and 1,, are made mutually opposite, either of the windings W and S can be used for all such actual applications as will be described hereinafter, exactly the same actions may be obtained by the use of the other basic logical circuits mentioned above.

A detailed description of the functioning principles of various examples of the basic logical circuit of this invention has been presented above. The method of assembling this basic logical circuit and carrying out logical operations will now be described.

First, in the case of constructing a shifting register, the output terminals T,, of the circuit of this invention, illustrated in FIGS. 1, 5, 8, and 9, are connected successively to the input terminals T, of the next stage in such a manner that the same polarities are connected with one another. These are divided into two groups I and II, and the currents I and I and I are made to flow, in sequence, through the windings and terminals of each group, with the respective phases of said currents lagged by one half cycle as indicated in I and II of FIG. 2 for the element of FIG. 1 and in I and II of FIG. 6 for the element of FIGS. 5, 8, and 9, and, at the same time, with synchronization so that the reading-out pulse current I, of the preceding stage and the writing-in bias pulse current I of the next stage will be impressed simultaneously, whereby the information can be shifted in order.-

FIG. 10 illustrates the case wherein the circuit of this invention illustrated in FIG. 5 has been connected in cascade formation. In FIG. 10, reference symbols I and II designate groups corresponding to I and II of FIG. 5, and I-l, II-1, I-2, II2, etc., designate the sequential numbers of the basic circuits belonging to the two groups.

Referring, first, to the driving pulse train of FIG. 6, if a resetting pulse current I of positive polarity flows, at an instant of time t through the winding S of the circuit belonging to the group I, the residual polarizations of the magnetic cores M M M and M become and respectively, as described previously. Then, if an input signal pulse current I, of positive or negative polarity, having information, is impressed at a time t from the preceding stage on the input winding I of the basic circuit I-l, a writing-in bias pulse current I of positive polarity flows simultaneously therewith in the winding W. Consequently, as described previously, the aforesaid magnetic cores assume polarities of and respectively, or and respectively, in accordance with the polarity of the current 1,, and said information is written in the magnetic cores of the circuit I-1 in the polarity pattern of their residual polarizations.

At a later time 1 the circuit belonging to the group II is reset by a resetting pulse current. Ata subsequent time t a reading-out pulse current I flows through the terminals R of the circuit of the group I, placing the magnetic cores of the group I in the condition of and respectively. If the circuit I-1 is written in by a current I, of positive polarity, an output pulse current I of positive polarity in accordance with the polarity of the current I, will be imposed with positive polarity from the output terminal T of the circuit I1 onto the input winding I of the circuit 11-1 of the group II. At this time, a writing-in bias pulse current I belonging to the group II will flow in the winding W of the circuit 11-1, and the magnetic cores of the circuit II-l will be written in the condition of and At a time 1 a resetting pulse current I of the group I flows in the winding S of the circuit I-1, and the aforesaid magnetic cores are returned to the conditions of and respectively. At a subsequent time l a reading-out pulse current flows through the terminals R of the circuit 11-1; and output current of positive polarity is imposed from the output terminal thereof to the input winding of the circuit I-2 of the next stage and, simultaneously, causes the aforesaid magnetic cores to assume the condition of and respectively. The circuit I-2, which has received an input pulse current of positive polarity, thus transmits its output to the circuit II-Z by the same process as in the circuit I-1, and an output pulse current I of positive polarity is obtained one half cycle later from the output terminals of the circuit 11-2. Of course, the polarity of this current I is the same positive polarity as that of the input signal pulse current of the circuit I-1. Further, it is similarly apparent that, if the polarity of the input signal pulse current of the circuit I-l is negative, the polarity of the output pulse current of the circuit 11-2 is negative. Consequently, it is possible to construct a shifting register in which an information signal is shifted successively from the group I to the group II and from the group II to the group I by the repetition of the operation wherein the information signal is shifted from the preceding stage to the next stage when unit logical circuits are connected in cascade formation as indicated in FIG. 10. Moreover, if the internal impedance of the reading-out pulse source is taken sufficiently high, the transmission of the information in the reverse direction can be completely suppressed by the reverse impedance of the rectifying elements.

It is also possible to classify the units into N classes in cyclic manner with respect to the cascade connection; that is if N=3, A, B, C; A, B, C, etc., then one would connect in parallel all the input ports of units of the same class, likewise the write-in ports of units of the same class would be in parallel. One would then make the phase of the input currents between adjacent classes l/N cycles apart, that is if N=3 the phase difference between the input current to a unit belonging to an A class and the input current to a unit belonging to either a B or C- class would be Likewise the write-in currents between adjacent units would have a phase difference of 120.

The case for a shifting register has been described above, but if, as shown in FIG. 11, the output terminals T and the input terminals T of the next stage are connected in reverse, the memory content of the preceding stage will be reversed in polarity as it is shifted to the succeeding stage, and a Not logical operation will be very simply effected.

If, as indicated in FIG. 12(a), three input windings 1, I and I with input terminals T T and T respectively, are provided, and, during writing-in, a current of constant amplitude and positive polarity, for example, as I is made to flow through the winding I in the direction of. from to of the terminal T it will be possible to write in the results of carrying out, on the input side by the principle of decision by majority, the logical operation of logical sum or OR of the logi- 9 cal variable currents I and I which, have the same amplitude as the current I or the operation of logical product or AND if a current of negative polarity is made to flow as the current I and said results being written in as residual magnetic flux in the aforementioned magnetic cores.

Said results may be taken out, by means of the reading-out current, by connecting a load Z to the output terminals, whereby an output pulse current of the logical sum, I =I +I or an output pulse current of the logical product, I =I -I can be taken out in the form of polarity of pulse current of constant amplitude. While the case of three inputs has been described above, it is apparent that the same operation of decision by majority is possible also for any odd number of inputs greater than three. Moreover, in any logical operation, said operation during writing in is carried out only on the input side, and, during reading out, the information content impressed as memory in the magnetic cores is merely read out as it is. Therefore, since it is possible to carry out only one cycle of logical operation with one control cycle of writing in and reading out, if a logical operation is to be carried out again with the information content which has been written in as the result of a prior logical operation, said written information content must first be read out, and then another logical variable must 'be added in the succeeding writing-in stage, and the logical operation is carried out thereafter. The aforementioned explanation relates to basic logical circuits applied to the case wherein pulse output current having positive and negative polarities. In the following will be described the case, in which a single current representing the binary digit and +1 or 0 and 1 is used as the input current.

Now, referring to FIG. 12(a) let it be assumed that to the input winding I 1, or I is impressed a signal input current I; of polarity or not impressed. In this case, it is possible to obtain an output load current I of polarity or polarity depending on whether the input current I of polarity is not applied or applied. Such operation can be carried out by connecting two of the three input windings 1 I and 1 in series, as illustrated in FIG. 12(1)).

In the circuit of FIG. 12(b), let it be assumed that a pulse signal current I corresponding to the binary digit 0 or +1 is impressed to said series windings I and I and another pulse signal current I having the same amplitude as the former current 1 is impressed, as the pulse signal current of polarity, to the winding I in the reverse direction. In this condition, if the current I is Zero, on the current L of polarity becomes pulse input current, so that a pulse output current I of polarity flows through the load Z On the contrary, if the pulse current I, of polarity is impressed, a pulse output current 1,, of polarity flows through the load Z because the same result as the case in which only one kind of pulse current of polarity is impressed to only one input winding is obtained by the decision by majority. When the pulse imput current 1, representing 0 or 1 is adopted, the same pulse output current as the aforementioned output current I will be obtained as long as the pulse current of positive polarity is used as the current 1, On the other hand, even when a direct current is used as the input current, the same output current as said current I will be obtained as long as the magnitude of said direct current is so selected that the magnetic flux densities of the magnetic cores do not exceed the coercive force H of said cores. The embodiment of FIG. 12(b) relates to the case wherein a pulse output current having positive or negative polarity is obtained by connecting a load Z to the output terminals T said load being usually an impedance of the input wind ing of the next stage. However, since, as described above in connection with the circuits of FIGS. 5, 7(a), and 7 (b), a directional pulse current flows or scarcely flows through the arms of the bridge depending'on whether the polarity of the pulse input current is or when one arm of the bridge is cut off and to this cut portion are provided output terminals, a pulse output current representing the binary digit 0, +1 or 0, 1 will be obtained at said output terminals. The embodiment of FIG. 12(c) relates to the case in which the circuit of FIG. 5 is used and between the output terminal T and the rectifying element D are, respectively, provided the single current output terminals +T T and +T T In this embodiment, the pulse output current obtained from the three output terminals T T and T corresponds to +1 at the terminal T and to 0 at the terminal T in the case of +1 at the terminal T and corresponds to 0 at the terminal T and to +1 at the terminal T in the case of 1 at the terminal T Consequently, when the adjacent arms of the bridge are, respectively, cut off at their respective intermediate portions, to these out portions are provided output terminals, and pulse output currents corresponding to 0, +1 and +1, 0 are used as the pulse input currents, pulse output currents of positive and negative polarities can be obtained by positively connecting one of two input windings of the next stage to the terminal T and by reversely connecting another of said windings as the Not connection.

By the circuit of this invention, in addition to the operation on the input side as above described, logical operations may be carried out also on the output side. As previously described with reference to FIGS. 4(a), 4(1)), 7(a), and 7 (b), since the output coils wound on the various magnetic cores are extremely similar to the contact points of mechanical relays, it is possible to enable logical operation in each of the writing-in and reading-out steps by combining, in conformity with the object, only the respective output coils wound on the magnetic cores of a number of the circuit belonging to the group I or group II, said output coils being divided and separated in an assembly of unit elements including one rectifying element, with a similarly divided and separated unit element of another circuit belonging to the same group, whereby two cycles of logical operation can be effected by one control cycle comprising writing-in and reading out. As a result, it is possible to increase substantially the speed of operation. At the same time, the same logical operation is effected with a smaller number of unit circuits than the necessary number thereof for operation on only the input side. The principle and functioning relating to the above circuits will be more apparent by reference to the following detailed description and the accompanying drawings.

FIG. 13 is a connection diagram showing one example of a winding arrangement constructed so as to obtain an output pulse current of logical sum based on the information content of two unit logical circuits during the reading out of the information content which has been written in as the result of a logical operation in which operation of decision by majority is effected simultaneously in both unit logical circuits during writing-in, that is, on the input side. In FIG. 13, M M M and M and Mal! M M and M are the various magnetic cores of the first circuit group I and the second circuit group II, respectively, and are provided with signal input windings, writing-in bias windings, reset windings, and output windings, respectively.

The signal input winding 1 1 I and 1 1 I the writing in bias windings W and W,,, and the reset windings S and S are connected similarly as in the circuit indicated in FIG. 12. However, only the output windings O and 0, have a rectifying element for each respective magnetic core, each series of elements being connected in series connection and separating into unit elements. The terminals 1 through 8 and 1a through 8a, of the unit elements are connected as in the drawing as follows: 1 to la and to 4, 2 to 2a and to 7a, 3 to 4a, 3a to 6a and to 6, 5 to 5a and to 8, and 7 to 8a; the reading-out pulse source terminals R and Ra are connected, respectively, to 2a or 7a and to 3a or 6a, In the ordinary case, the load Z is substituted for the input winding of the next stage.

FIG. 14 illustrate-s an arrangement wherein the output circuits have been substituted by the functioning of the contact points of mechanical relays similarly as in the illustrations indicated previously, and wherein A, B, C, and D represent four arms if the bridge and Ua and Ila have the same functioning capacities as U and Tl, respectively, as described above. In the case when an information is to be written into the first and second unit logical circuits wherein the output windings have been divided and separated and reconnected anew, or in the case of resetting, these operations are carried out in exactly the same manner as described with reference to FIG. 5, and the reaction current due to the counter voltage induced on the output side is completely suppressed by the internal impedances of the reading-out pulse source and the reverse resistance of the rectifying elements, which suppression is the same as in the case illustrated in FIG. 5.

If, in the first circuit, that is, of the cores M M M and M side, the condition wherein an information signal has been written into said magnetic cores by three signal input currents I 1, I and a writing-in bias current I is represented by X, and that of the second circuit, that is, of the cores M M M and M side is represented by Y, the designation of X and Y by or means that the magnetic fields of respective magnetic cores are all in the or condition. Accordingly, the reading-out mechanism for the cases wherein said X and Y are respectively, combined will be described below.

(1) When X and Y are both in the condition. That is, it with the cores M M M and M and M M M 3, and M written in the condition of and a reading-out pulse current I is made to flow in the direction of from to of the reading-out terminals 'R, the respective output coils would on the cores M M and M M in which the direction of flow of the current 1, becomes coincident with respect to the polarity of the residual flux density of the magnetic cores will offer lower impedance against the current 1,. Consequently, this reading-out pulse current I flows principally in the direction of: Reading-out pulse source terminal R 4+ 3 441+ 3a T -e Z T,, 7a- 8a- 7 8+ 'R,, and an output pulse current I of negative polarity as indicated by the dotted-line arrow is taken out in load A If the polarity of the output pulse current is expressed by symbol Z, Z is in the above case.

(2) When X is in the condition, and Y is in the condition. That is, when the cores M M M and M are written in the conditions of and respectively, the output coils wound on the cores M M and M M present high impedance against the current 1,, and the output coils wound on the cores M M and M g, M present low impedance against the current 1,. Consequently, the current I flows principally in the direction of: +R 1a 2a T Z T,, 6ae5aeRa, and an output pulse current of positive polarity as indicated by the full line arrow is obtained at the load Z Accordingly, Z is in this case.

(3) When X is the condition, and Y is in the condition. That is, in this case, the output coils wound on the cores M M and M M g oifer high impedance against the current I, and the output coils wound on the cores M M and M M offer low impedance against the current 1,. Consequently, the current I flows principally in the direction of +R 1 2 Z T 6 5 Ru, and at the load 2 an output pulse current of positive polarity is obtained, similarly as in the preceding case 2. Accordingly, Z is (4) When X and Y are both in the condition.

12 In this case, the output coils Wound on the cores M M and M M,, oifer high impedance against the current 1,, and the output coils wound on the cores M M and M M g offer low impedance against the current 1,.

Consequently, the current I flows principally in the direction of: +R 1, 111-92, 2a T,, Z T,, 6, 6a+5, 5a -Ra, and, in this case also, an output pulse current of positive polarity is obtained at the load Z Accordingly, Z is I.

Now, if the conditions which have been written in the first and second circuits in the state of X and Y and the polarity of the output pulse current I, taken out at the load Z by impressing a reading-out pulse current I on these conditions, that is Z, are represented for each of the above cases, a pattern as shown in Table 1(a) results. Further, if the and symbols which indicate these polarities are made to correspond to 1 and 0 of binary digits, a pattern as shown in Table l(b) results.

Table 1(a) Table 1(b) l X Y Z i X Y i Z I These tables, in other words, indicate that the polarity Z of the output pulse current is extracted as the result of carrying out, during the reading out of the written-in conditions of the condition X of the first circuit and the condition Y of the second circuit, the operation of the logical sum Z=X+Y of the said conditions X and Y, with said X and Y as logical variables.

After the information written in the respective magnetic cores has been read out in the above manner, both the first and second circuits assume the condition of and respectively. Then, by causing a reset pulse current I to flow in the windings S and 8,, said circuits are returned to the original condition of and The possibility of carrying out successive logical operations by the repetition of the same steps as described above is the same as in the case of using the circuit of FIG. 12 in the form shown, and, in general, both are used in suitable combination. Furthermore, the purpose of inserting the rectifying elements D through D, and D through D,,.,, which are connected in series in their respective output windings, that is, to suppress the current which flows through the output winding side during writing in and in the case of resetting and, thereby, to enable efiicient writing in and resetting i the same as has been described previously. In this case however, either D and D or D and D may be omitted without causing detrimental effect on the functions of writing in and resetting. In the general case, the load Z is substituted by the input winding of the next stage, and the output pulse current L, is imposed to the input winding of the next stage as a signal input pulse current, in the same Way as was described with reference to FIG. 5. The slight difference in the amplitude of the output pulse current with respect to the four kinds of combinations of X and Y, as indicated in Table 1 (a) or (b), can be remedied fully by using magnetic cores having an excellent rectangular characteristics and coercive force H, of low magnitude.

The above description relates to the case wherein logical sum is carried out on the output side Next, another example indicated in FIG. 15, of logical operation on the output side, the case of carrying out logical multiplication or product, will now be described.

Referring to FIG. 15, while the directions of the windings with respect to their respective magnetic cores are exactly the same as in the case of FIG 13, only the connections of the respective terminals of the output windings are different, that is, the connections of the points 1 through 8 and 1a through St: and the terminals +R and Ra are as follows: 1 to 7 and 7a, 2 'to 1a, 2a to 4a and 4, 3 to 3a and 5, 6 to 5m, and 6a to 8a and 8; the readingout pulse source terminals +R and Ra are connected, respectively, to 1, 7 and 3, 5; and the output terminals T and T are connected, respectively, to 2a, 4a and 6a, 8a. Thus, the steps of operation of this circuit arrangement are exactly the same as those of the case illustrated in FIG. 13 in that for example: a resetting pulse current I is made to flow through the reset windings S and S of the first circuit I and the second circuit II to reset the respective circuits: a writing-in bias pulse current I is made to flow through the writing-in bias windings Wand W and signal input pulse currents I I 1 and I I L are made to flow, respectively, through the signal input 1N1, IN), 1N3, and I b I g, l g, Of the respective circuits to effect logical operation on the input side; writing-in as the result thereof, is carried out in the form of or polarity, in the first circuit and the second circuit; and the reaction current which flows through the output side during resetting and writing-in is completely suppressed by the internal impedance of the reading-out pulse source and the reverse resistance of the rectifying elements Therefore, similarly as in the case illust ated in FIG. 13, the case of reading out will be described below with X representing the written-in condition of the first circuit and Y representing the written-in condition of the second circuit.

FIG. 16 illustrates, similarly as does FIG. 14, the output circuit as being represented by -U, Ua, U, and fizz, corresponding to the functioning of the contact points of mechanical relays.

(1) When both X and Y are in the condition. In this case, if a reading-out pulse current I, is made to flow through the terminals +R and Ra, the output coils wound on the cores M M and M M offer high impedance against said current 1,, and the output coils wound on the cores M M and M M offer low impedance against the same. Consequently, the current I flows principally in the direction of: Reading-out pulse source terminal +R 7, 7a 8, 8a T Z T 4, 4a 3, 3a -Ra, and an output pulse current L, of negative polarity is obtained at the load Z Accordingly if the polarity of the current I is expressed by symbol Z in the same manner as in the case of FIG. 13 Z is (2) When XX is in the and Y is in the condition. In this case, the cores M M and M M offer high impedance against the current 1,, and the cores M M and M M offer low impedance against the current 1,. Consequently the current I flows principally in the direction of: +R- 7- 8 T Z T 4 3+ Ra, and since an output pulse current of polarity is obtained as before, Z is (3) When X is in the and Y is in the condition. In this case, the cores M M and M M g offer high impedance against the current 1,, and cores M M and M82: M offer low impedance against the current I Consequently the current I, flows principally in the direction of: +R 7a 8a T., Z T 4a 3a .-Ra, and since an output pulse current of polarity is obtained as before, Z is (4) When both X and Y are in the condition. In this case, the cores M M and M M offer high impedance against the current I and the cores M M and M M offer low impedance against the current I Consequently the current I flows principally in the direction of:

and an output pulse current I of polarity is obtained at the load Z Accordingly, Z is Now as all the above cases are represented in the same manner as in the case illustrated in FIG. 13, Table 2(a) and Table 2(1)) result.

Table 2(a) Table 2(b) X Y Z X Y Z These tables indicate that the output pulse current I is taken out as the result of carrying out, during the reading out of the written-in conditions of the first circuit side, that is, X, and of the second circuit, that is Y, the operation of the logical product Z =X Y of the said conditions X and Y, with said X and Y as logical variables.

In this case also, the fact that either the cores D and D or D and D may be omitted without causing detrimental effect on the functions of writing-in and resetting, and the fact that the same is true even with the use of a basic circuit other than that of FIG. 5, that is, the circuit of FIG. 8 or FIG. 9, etc., is the same as in the case relating to FIG. 13. Moreover, in the case wherein operation is to be carried out on the output side in a circult using two magnetic cores of and two rectifying elements as in case of FIG. 1, it is possible to carry out operation on the output side in exactly the same manner as described before, by using, as the first and second circuits, two of each; connecting in series, input windings in each of the first and second circuits; dividing and separating the output winding side into uni-t elements similarly as in the aforedescribed case; and connecting the same in the forms as indicated in FIGS. 13 and 15. In other words, the number of output windings including the unit elements, that is, the rectifying elements, is the same in either case.

Of course, the output pulse current resulting from operation carried out on the output side may be used also as the input pulse current of the circuit using two magnetic cores and rectifying elements.

The cases wherein operations of logical sum and logical product are effected on the output side during reading out have been described above.

It will be appreciated that both the AND and OR circuits have two units of the four magnetic element logic units. That the output couplings and diodes of the corresponding magnetic elements of the units are connected alternately in series and in parallel. That is if the output couplings of the first elements are in parallel, the output couplings of the second units are in series, the third are in parallel, the fourth in series. If the first elements are in series the sequence is reversed. These connections form sequential pairs of output couplings. The first pair formed from the first elements, the second pair from the second elements, etc. Then two pairs are connected to the plus read-out terminal and the two remaining pairs to the minus read-out terminals. Then two pairs are picked without consideration of the pairs connected to the read-out terminal, these new pairs are connected to the plus and minus output terminals respectively.

A further example is described below:

FIG. 17 illustrates an example of operation on the output side, which, with the use of four sets of the basic logical circuit of FIG. 12, carries out the action of Full Adder in one operation during the reading out of the information content which has been written in the form of the polarities of the magnetic cores of the respective circuits. That is, let the input windings of the circuit be designated, respectively, by I I and I let the signal input currents which are imposed simultaneously on said windings in the four circuits be designated by x, y and z; and let it be supposed that said currents are imposed with polarities and equal amplitudes in the direction of from to to said input windings. Similarly as in the cases of FIGS. 13 and 15, a current I is caused to be imposed to the writing-in bias windings W, and a current is caused to be imposed to the reset windings S, these currents being made to take place simultaneously in the four circuits. On the output side, let the output terminals be, respectively, T T T T T T303, T T let their connections be T to T T to T T to T and T to T in addition let T be connected to T and T to T and let a load Z be connected between T and T Let the polarity of the output pulse current I flowing through the load Z be designated by w, and let the current I which flows in the direction of from T to T be of positive polarity and from T to T be of negative polarity. Further, as the reading-out pulse currents, let the current I be made to flow, with respect to the circuits E E from the terminal +R of the circuit E to the terminal -R,, of the circuit E and let the current I be made to flow, with respect to circuits E E from the terminal +R of the cincuit E to the terminal -R,, of the circuit E whereby both amplitudes of I and 1,, are caused to be equal. Let it be supposed that current is prevented from flowing from R to R,, or R to R that is, two reading-out pulse sources having terminals R R and R and R are different. The output circuits of FIG. 17 are represented in FIG. 18 by U U U U and E, E T7 F let it be supposed that these, in this case also, have, respectively, the same functioning capacities as U, fi described previously. In FIG. 18, A, B, C, and D, and Au, Ba, Ca, and Da are, respectively, four arms of one of two bridges the output terminals of which are made common.

Now, the symbol which-assumes when signal input currents x, y, z are imposed in various combinations of or will be studied.

(1) When x, y, z are all Since in the circuit E all of the signal input windings are Not, and the signal input currents x, y, and z are all the signals will be written in the condition. Since in the circuit E the signal input windings I and I are positive, and only I is Not, the signals will be written in the condition. Since in the circuit E I is Not, and the currents I and I are positive, the signals will be written in the condition. If, with the circuits written in such conditions as above-described, reading out pulse currents I and I of equal amplitude, are made to flow simultaneously through the terminals R R and R R g of the readingout pulse sources, coils wound on the cores M M will offer high impedance, and the coils wound on the cores M M will offer low impedance within the output windings against the current 1,. Consequently, the greater part of the current I, will flow in the direction of R T T R and almost none will flow in the load Z On the other hand, the coils wound on the cores M M will oifer high impedance, and the coils wound on the cores M M will offer low impedance against the current I Consequently, the greater part of the 1,, will flow in the direction of R T,, T T Z T R,, and an output pulse current will flow in the load Z in the direction from to Accordingly, w, which indicated the polarity of the current I is (2) When x and y are and z is In this case, the circuits E E E and E, are written in, respectively, as and If, with the said circuits in the said conditions, reading-out pulse currents I and 1 are made to flow, respectively, through the reading-out terminals R R and R R g, the coil wound on the cores M M will oifer high impedance, and the coils wound on the cores M 4, M1 will offer low impedance, in the respective output windings against the current 1,. Consequently the greater part of the current I will flow in the direction of R T T -+Z T,, R On the other hand, the coils wound on the cores M M will otter high impedance, and the coils wound on the cores M M will offer low impedance against the current I Consequently, the greater part of the current 1,, will flow in the direction of R, T T +R and hardly any will flow through the load Z As a result, the output pulse current I which is the greater part of the current I will flow in the negative direction through the load Z Accordingly, w will become (3) When x is and y and z are In this case,

the circuits E E and E are written in the condition of and the circuit E in the condition of As a result, the coils wound on the cores M M will offer high impedance, and the coils wound on the cores M M will offer low impedance, within the output windings of the respective circuits against the current 1,. Consequently, the greater part of the current I will flow in the direction of R T T,, Z +T,, R On the other hand, the coils wound on the cores M M will offer high impedance, and the coils wound on the cores M M will otter low impedance, against the current I Consequently, the greater part of the current I will flow in the direction of R +T T,, R and hardly any will flow through the load Z As a result, the output pulse current I due to the greater part of the current I will flow through the load Z in the positive direction. Accordingly, w will be (4) When 16, y, z are all In this case, the circuit E is written in as and the other circuits E E B are written in as As a result, the coils wound on the cores M M will offer high impedance, and the coils wound on the cores M M will offer low impedance, within the output windings of the respective circuits, against the current 1,. Consequently, the greater part of the current I will flow in the direction of R T,, R,, and almost none will flow through the impedance Z On the other hand, the coils wound on the cores M M will otter high impedance, and the coils wound on the cores M M will offer low impedance against the current I Consequently, the greater part of the current L, will flow in the direction of R +T +T Z T,, eR,, As a result, the output pulse current I which is the greater part of the current I will flow through the load Z in the negative direction. Accordingly, w is If, now, the relations between the symbols of the input currents, the polarities of the circuits E E E and E and the symbol of w of the output current are tabulated, Table 3(a) will be produced. Further, if the and symbols of the input and output currents are made to correspond to 1 and 0 of binary digit, Table 3(b) will be produced.

With respect to combinations other than those of x, y, and 1 indicated in Table 3(b) may be tried in the above described manner. Table 3(b) indicates that the circuit of FIG, 17 'P SSQSSQS the function of a Full Adder.

17 While in the case of FIG. 17, the case is illustrated wherein the circuit elements with four magnetic cores and diodes are used, it is apparent from FIG. 17 or FIG. 18 that, since only a half of the circuit elements is suflicient, it is possible to divide and separate the output sides of unit logical circuits which are provided with the two mag netic cores and diodes indicated in FIG. 1, to reconnect the same suitable, and to construct Full Adder similar to that of FIG. 17. Furthermore, in the embodying of this invention, when a pulse output current caused by a logical operation at the output side is used as the pulse input current of the next state, Not operation can be, as described above, easily attained by reverse connection of the output terminals of the next stage.

The logical operation of And, Or, and Full Adder at the output side have been described hereinbefore. However, any person having an ability capable of constructing a relay circuit by use of mechanical relays can easily construct the following various complex logical circuits by application of the logical circuit of this invention.

For example, the logical function such as shown by the equation can be easily embodied by the circuit as shown in FIG. 19. In the circuit of FIG. 19 input, writing-in bias, and resetting windings are omitted; the circuit I, comprises output windings L L L and L and rectifying elements D D D and D and is written in with the input signal corresponding to X the circuit II comprises output windings L L L and L and rectifying element D and D and is written in with the input signal'corresponding to X the circuit III comprises output windings L L L and L and rectifying elements D and D and is written in with the input signal corresponding to X and the circuit IV comprises output windings L L L and L and rectifying elements D and D and is written in with the input signal corresponding to X FIG. 20 represents the equivalent circuit diagram in which contact points U11, E1 T713, T514, U21, T322, U23, F U If U F 41, U F of mechanical relays have been substituted for the outpost windings L L14, 1121 L24, L31 L34, L41 L44- FIG. 21 shows a modification of the relay circuit of FIG. 20, the operation of the circuit of FIG. 21 being entirely the same as that of the circuit of FIG. 20.

The rectifying elements used in the circuit of FIG. 21 act to give directivity to the pulse currents.

FIG. 22 shows an actual logical circuit for carrying out the logical function.

FIG. 23 shows the equivalent diagram of the circuit of FIG. 22, in which the contact points of mechanical relays have been substituted for the output windings.

FIG. 24 shows a modification of the relay circuit of FIG. 23.

In FIGS. 22, 23, and 24, the same members are, respectively, designated by the same symbols'as those in FIGS. 19, 20, and 21.

Here, g, h may be taken to be a binary digit representing 0 or 1.

The sum D or G and H may be expressed as and the adder determining d, from g, and H can deter- 75 1'8 mine d, from the following Equation 1 by use of the following relations 2:

Here, C is unknown until C C C -1 have been determined in order. Consequently, in the case of an adder which carries out such additions in parallel at high speed, a high-speed, carry detector which quickly determines C C 0,, becomes necessary. However, the logical circuit for this purpose ordinarily requires an extremely large number of elements and, moreover, requires a considerable long period of time. Yet, it is known that, in the relay circuits, a carry detector capable of instantaneously detecting carry by the circuit illustrated in FIG. 24, wherein C C1,; C 6 C 6,, can be determined from the fact that they are obtained as electric currents representing their respective logical functions at the portions indicated by the arrows in the illustrations. Furthermore, the circuits which can be constructed by such a combination of relays as described above can all be composed from thelogical circuit of this invention as previously described.

Accordingly, by composing the same circuit as in FIG. 25 by the use of the logical circuit of this invention and, as indicated therein, by connecting the lines of C and G to the input winding of the circuit of the next stage, C C C C can be obtained immediately. By the present invention, a high speed carry detector of 11 digits can be composed from only 311 logical elements. Said number cannot be realized, by any means, with other kinds of logical circuits. Moreover, this circuit is seriesconnected in ladder formation, and C C can be obtained from many points of the ladder.

Therefore, by combining said carry detector and the Full adder described with reference to FIG. 17, it is possible to carry out extremely high-speed additions of n digits.

The fact that, by the use of the logical circuit of this invention as described above, various kinds of complicated logical operations are realized at extremely high speed and, moreover, with a small number of elements, is of exceedingly great interest.

As has been described above in detail, the logical operation circuit of this invention is one in which, an even number of magnetic cores having rectangular hysteresis characteristics is taken as one group; the magnetic cores are provided with windings and combined with rectifying elements; a reading-out pulse current is made to flow directly in the output windings and the input winding of the next state, without the use of such means as a transformer for the input or output; andthe writing in and reading out of information signals are made to take place by utilizing the directional changes of the residual mag? netic fluxes of the magnetic cores. Therefore, it is possible to make the output pulse flow always with constant amplitude without floating of its basic level. Furthermore, the output circuit is in the form of a bridge; the load impedance, as viewed from the power resource for reading-out, does not change in accordance with the writingin condition; a reading-out pulse current of constant amplitude can be always supplied to the circuit; and it is possible to effect sure and accurate logical operations. Moreover, since the logical operation circuit of this invention is composed of a combination of only magnetic cores and rectifying elements, it is possible to raise the operation speed up to the limit set by the overheating of the magnetic cores and the current capacities of the rectifying elements. Since the output circuit is in the form of a 

1. A LOGIC CIRCUIT COMPRISING A PLURALITY OF LOGIC UNITS EACH UNIT COMPRISING FOUR MAGNETIC ELEMENTS EACH HAVING SUBSTANTIALLY RECTANGULAR HYSTERSIS CHARACTERISTICS, EACH OF THE ELEMENTS HAVING THREE KINDS OF COUPLINGS NAMELY, AN EQUAL ODD NUMBER OF INPUT COUPLINGS, A WRITE-IN COUPLING, AND AN OUTPUT COUPLING; THE WRITE-IN AND OUTPUT COUPINGS BEING CONNECTED IN SERIES RESPECTIVELY TO FORM WRITE-IN AND OUTPUT PORTS, MEANS CONNECTING ONE INPUT COUPLING FROM EACH ELEMENT IN SERIES WITH ONE ANOTHER TO FORM A PLURALITY OF RESPECTIVE INPUT PORTS THE SAME IN NUMBER AS THERE ARE INPUT COUPLINGS ON AN ELEMENT; ALL THE COUPLINGS OF ONE ELEMENT BEING COUPLED TO MAGNETIZE IN THE SAME DIRECTION, ONE OF THE THREE KINDS OF COUPLINGS ON EACH OF THE REMAINING ELEMENTS BEING REVERSELY COUPLED WITH RESPECT TO OTHER TWO KINDS OF COUPLINGS ON THE SAME ELEMENT AND EACH OF THE THREE KINDS OF PORTS INCLUDING ONE OF SAID REVERSELY COUPLED COUPLINGS, MEANS FOR APPLYING A RESETTING PULSE CURRENT HAVING AMPLITUDE SUFFICIENT TO SATURATE THE ELEMENTS TO A RESET PORT TO SET THE UNIT TO INITIAL STATES OF MAGNETIZATION, THE RESET PORT COMPRISING FOUR COUPLINGS COUPLED RESPECTIVELY TO THE FOUR ELEMENTS AND CONNECTED IN SERIES, MEANS FOR THEREAFTER APPLYING A WRITE-IN PULSE CURRENT TO THE WRITE-IN PORT HAVING AMPLITUDE EQUAL TO THE COERCIVE FORCE OF THE ELEMENTS, THE WRITE-IN COUPLING AND THE RESET COUPLING ON EACH OF THE ELEMENTS MAGNETIZING EACH ELEMENT IN OPPOSITE POLARITIES, MEANS FOR APPLYING INPUT PULSE CURRENT TO AT LEAST ONE OF THE INPUT PORTS SIMULTANEOUSLY WITH THE APPLICATION OF THE WRITE-IN PULSE; THE OUTPUT PORT CONNECTED IN A CLOSED LOOP TO FORM A BRIDGE EACH OUTPUT COUPLING BEING AN ARM OF THE BRIDGE, WITH JUNCTIONS BETWEEN THE ARMS, TWO OPPOSED JUNCTIONS OF THE BRIDGE BEING PLUS AND MINUS OUTPUT TERMINALS RESPECTIVELY, THE REMAINING TWO JUNCTIONS BEING PLUS AND MINUS READOUT TERMINALS RESPECTIVELY; FOUR RECTIFYING ELEMENTS CONNECTED IN SERIES WITH THE OUTPUT COUPLINGS RESPECTIVELY THE FORWARD DIRECTION OF THE RECTIFYING ELEMENTS BEING FROM PLUS TO MINUS OF THE READOUT TERMINALS; MEANS FOR APPLYING A READOUT PULSE CURRENT TO THE READOUT TERMINALS CAUSING AN OUTPUT SIGNAL TO EXIST AT THE OUTPUT TERMINALS AND THUS RETRIEVING THE INFORMATION STORED INTO THE UNIT BY THE INPUT CURRENT; MEANS CONNECTING THE OUTPUT PORT OF ALL BUT ONE UNIT TO THE INPUT PORT OF ANOTHER UNIT IN CASCADE FASHION WHEREBY A SHIFT REGISTER IS FORMED. 